CD4541B programmable timer consists of a 16-stage binary counter, an oscillator that is controlled by external R-C components (2 resistors and a capacitor), an automatic power-on reset circuit, and output control logic. The counter increments on positive-edge clock transitions and can also be reset via the MASTER RESET input.

The output from this timer is the Q or Q\ output from the 8th, 10th, 13th, or 16th counter stage. The desired stage is chosen using time-select inputs A and B (see Frequency Select Table).

The output is available in either of two modes selectable via the MODE input, pin 10 (see Truth Table). When this MODE input is a logic "1", the output will be a continuous square wave having a frequency equal to the oscillator frequency divided by 2^N. With the MODE input set to logic "0" and after a MASTER RESET is initiated, the output (assuming Q output has been selected) changes from a low to a high state after 2^N-1 counts and remains in that state until another MASTER RESET pulse is applied or the MODE input is set to a logic "1".

Timing is initialized by setting the AUTO RESET input (pin 5) to logic "0" and turning power on. If pin 5 is set to logic "1", the AUTO RESET circuit is disabled and counting will not start until after a positive MASTER RESET pulse is applied and returns to a low level. The AUTO RESET consumes an appreciable amount of power and should not be used if low-power operation is desired. For reliable automatic power-on reset, V_DD should be greater than 5V.

The RC oscillator, shown in Figure 2, oscillates with a frequency determined by the RC network and is calculated using:

Where f is between 1kHz and 100kHz and R_S and 2R_TC.

• Low Symmetrical Output Resistance, Typically 100 at VDD = 15V
• Built-In Low-Power RC Oscillator
• Oscillator Frequency Range . . . DC to 100kHz
• External Clock (Applied to Pin 3) can be Used Instead of Oscillator
• Operates as 2 N Frequency Divider or as a Single-Transition Timer
• Q/Q\ Select Provides Output Logic Level Flexibility
• AUTO or MASTER RESET Disables Oscillator During Reset to Reduce Power Dissipation
• Operates With Very Slow Clock Rise and Fall Times
• Capable of Driving Six Low Power TTL Loads, Three Low-Power Schottky Loads, or Six HTL Loads Over the Rated Temperature Range
• Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• 5V, 10V, and 15V Parametric Ratings
• Meets All Requirements of JEDEC Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"

Data sheet acquired from Harris Semiconductor

• Technology Family
• CD4000
• Bits (#)
• 1
• Supply voltage (Min) (V)
• 3
• Supply voltage (Max) (V)
• 18
• Input type
• Standard CMOS
• Output type
• Push-Pull
• ICC (Max) (uA)
• 100
• IOL (Max) (mA)
• 4
• IOH (Max) (mA)
• -4

CD4541B的完整型号有：CD4541BE、CD4541BM、CD4541BM96、CD4541BMT、CD4541BNSR、CD4541BPW、CD4541BPWR、CD4541BPWRG4，以下是这些产品的关键参数及官网采购报价：

CD4541BE，工作温度：-55 to 125，封装：PDIP (N)-14，包装数量MPQ：25个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：NIPDAU，TI官网CD4541BE的批量USD价格：0.23（1000+）

CD4541BM，工作温度：-55 to 125，封装：SOIC (D)-14，包装数量MPQ：50个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD4541BM的批量USD价格：0.26（1000+）

CD4541BM96，工作温度：-55 to 125，封装：SOIC (D)-14，包装数量MPQ：2500个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD4541BM96的批量USD价格：0.126（1000+）

CD4541BMT，工作温度：-55 to 125，封装：SOIC (D)-14，包装数量MPQ：250个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD4541BMT的批量USD价格：0.26（1000+）

CD4541BNSR，工作温度：-55 to 125，封装：SO (NS)-14，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD4541BNSR的批量USD价格：0.24（1000+）

CD4541BPW，工作温度：-55 to 125，封装：TSSOP (PW)-14，包装数量MPQ：90个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD4541BPW的批量USD价格：0.26（1000+）

CD4541BPWR，工作温度：-55 to 125，封装：TSSOP (PW)-14，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD4541BPWR的批量USD价格：0.139（1000+）

CD4541BPWRG4，工作温度：-55 to 125，封装：TSSOP (PW)-14，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD4541BPWRG4的批量USD价格：0.25（1000+）

14-24-LOGIC-EVM — 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。