This positive-edge-triggered D-type flip-flop has a direct clear (CLR)\ input. The CD74AC175 features complementary outputs from each flip-flop.

Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output.

• AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage
• Buffered Inputs
• Contains Four Flip-Flops With Double-Rail Outputs
• Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
• Balanced Propagation Delays
• ±24-mA Output Drive Current
  • Fanout to 15 F Devices
• SCR-Latchup-Resistant CMOS Process and Circuit Design
• Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015
• Applications Include:
  • Buffer/Storage Registers
  • Shift Registers
  • Pattern Generators

• Number of channels (#)
• 4
• Technology Family
• AC
• Supply voltage (Min) (V)
• 1.5
• Supply voltage (Max) (V)
• 5.5
• Input type
• Standard CMOS
• Output type
• Push-Pull
• Clock Frequency (Max) (MHz)
• 100
• IOL (Max) (mA)
• 24
• IOH (Max) (mA)
• -24
• ICC (Max) (uA)
• 160
• Features
• Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

CD74AC175的完整型号有：CD74AC175M、CD74AC175M96，以下是这些产品的关键参数及官网采购报价：

CD74AC175M，工作温度：-55 to 125，封装：SOIC (D)-16，包装数量MPQ：40个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD74AC175M的批量USD价格：0.439（1000+）

CD74AC175M96，工作温度：-55 to 125，封装：SOIC (D)-16，包装数量MPQ：2500个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD74AC175M96的批量USD价格：0.239（1000+）

14-24-LOGIC-EVM 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。