The SN74AHC595 contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage registers. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output for cascading. When the output-enable (OE) input is high, all outputs, except Q_H', are in the high-impedance state.

Both the shift-register clock (SRCLK) and storage-register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register.

• Qualified for Automotive Applications
• Operating Range 2-V to 5.5-V VCC
• 8-Bit Serial-In, Parallel-Out Shift
• Shift Register Has Direct Clear

• Configuration
• Serial-in, Parallel-out
• Bits (#)
• 8
• Technology Family
• AHC
• Supply voltage (Min) (V)
• 2
• Supply voltage (Max) (V)
• 5.5
• Input type
• Standard CMOS
• Output type
• 3-State
• Clock Frequency (MHz)
• 80
• IOL (Max) (mA)
• 8
• IOH (Max) (mA)
• -8
• ICC (Max) (uA)
• 40
• Features
• Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs, Output register

SN74AHC595-Q1的完整型号有：SN74AHC595QPWRQ1，以下是这些产品的关键参数及官网采购报价：

SN74AHC595QPWRQ1，工作温度：-40 to 125，封装：TSSOP (PW)-16，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74AHC595QPWRQ1的批量USD价格：.211（1000+）

14-24-LOGIC-EVM 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。