This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V V_CC operation.

Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\) and clock-enable (CLKENBA\) inputs. For the A-to-B data flow, the data flows through a single buffer. The B-to-A data can flow through a four-stage pipeline register path, or through a single register path, depending on the state of the select (SEL\) input.

Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input, provided that the appropriate CLKENBA\ input is low. The B-to-A data transfer is synchronized with CLK.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

• Member of the Texas Instruments Widebus Family
• UBT Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enable Mode
• Operates From 1.65-V to 3.6-V
• Max tpd of 3.2 ns at 3.3-V
• ±24-mA Output Drive at 3.3-V
• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• ESD Performance Tested Per JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)

Widebus, UBT are trademarks of Texas Instruments.

• IOL (Max) (mA)
• 24
• IOH (Max) (mA)
• -24
• Technology Family
• ALVC
• Rating
• Catalog
• Operating temperature range (C)
• -40 to 85

SN74ALVCH16524的完整型号有：SN74ALVCH16524DL，以下是这些产品的关键参数及官网采购报价：

SN74ALVCH16524DL，工作温度：-40 to 85，封装：SSOP (DL)-56，包装数量MPQ：20个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74ALVCH16524DL的批量USD价格：4.784（1000+）