The SN54AS286 and SN74AS286 universal 9-bit parity generators/checkers feature a local output for parity checking and a 48-mA bus-driving
parity input/output (I/O) port for parity generation/checking. The word-length capability is easily expanded by cascading.

The transmit () control input is implemented specifically to accommodate cascading. When is low, the parity tree is disabled and PARITY ERROR remains at a high logic level regardless of the input levels. When is high, the parity tree is enabled. PARITY ERROR indicates a parity error when either an even number of inputs (A-I) are high and PARITY I/O is forced to a low logic level, or when an odd number of inputs are high and PARITY I/O is forced to a high logic level.

The I/O control circuitry was designed so that the I/O port remains in the high-impedance state during power up or power down to prevent bus glitches.

The SN54AS286 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS286 is characterized for operation from 0°C to 70°C.

• Generate Either Odd or Even Parity forNine Data Lines
• Cascadable for n-Bit Parity
• Direct Bus Connection for Parity Generation or Checking by Using the Parity I/O Port
• Glitch-Free Bus During Power Up/Down
• Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

• Number of channels (#)
• 9
• Technology Family
• AS
• Input type
• Bipolar
• Output type
• Push-Pull
• Features
• Very high speed (tpd 5-10ns)

SN74AS286的完整型号有：SN74AS286D、SN74AS286N，以下是这些产品的关键参数及官网采购报价：

SN74AS286D，工作温度：0 to 70，封装：SOIC (D)-14，包装数量MPQ：50个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74AS286D的批量USD价格：1.495（1000+）

SN74AS286N，工作温度：0 to 70，封装：PDIP (N)-14，包装数量MPQ：25个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：NIPDAU，TI官网SN74AS286N的批量USD价格：1.719（1000+）

14-24-LOGIC-EVM 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。