The SN74F543 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable ( or ) and output enable ( or ) inputs are provided for each register to permit independent control in either direction of data flow. The A outputs are characterized to sink 24 mA while the B outputs are characterized to sink 64 mA.

The A-to-B enable () input must be low in order to enter data from A or to output data from B. Having low and low makes the A-to-B latches transparent; a subsequent low-to-high transition of puts the A latches in the storage mode. With and both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar, but requires using the , , and inputs.

The SN74F543 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area.

The SN74F543 is characterized for operation from 0°C to 70°C.

A-to-B data flow is shown; B-to-A flow control is the same except that it uses , , and .

Output level before the indicated steady-state input conditions were established.

• 3-State True Outputs
• Back-to-Back Registers for Storage
• Package Options Include Plastic Small-Outline and Shrink Small-Outline Packages and Standard Plastic 300-mil DIPs

• IOL (Max) (mA)
• 64
• IOH (Max) (mA)
• -15
• Technology Family
• F
• Rating
• Catalog
• Operating temperature range (C)
• 0 to 70

SN74F543的完整型号有：SN74F543DBR、SN74F543DW、SN74F543DWR，以下是这些产品的关键参数及官网采购报价：

SN74F543DBR，工作温度：0 to 70，封装：SSOP (DB)-24，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74F543DBR的批量USD价格：.457（1000+）

SN74F543DW，工作温度：0 to 70，封装：SOIC (DW)-24，包装数量MPQ：25个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74F543DW的批量USD价格：.498（1000+）

SN74F543DWR，工作温度：0 to 70，封装：SOIC (DW)-24，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74F543DWR的批量USD价格：.415（1000+）

14-24-LOGIC-EVM 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。