The '107 contain two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. The '107 is a positive pulse-triggered flip-flop. The J-K input data is loaded into the master while the clock is high and transferred to the slave and the outputs on the high-to-low clock transition. For these devices the J and K inputs must be stable while the clock is high.

The 'LS107A contain two independent negative-edge-triggered flip-flops. The J and K inputs must be stable prior to the high-to-low clock transition for predictable operation. When the clear is low, it overrides the clock and data inputs forcing the Q output low and the Q\ output high.

The SN54107 and the SN54LS107A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74107 and the SN74LS107A are characterized for operation from 0°C to 70°C.

• Package Options Include Plastic “Small Outline" Packages, Ceramic Chip Carriers, and Plastic and Ceramic DIPs
• Dependable Texas Instruments Quality and Reliability

• Number of channels (#)
• 2
• Technology Family
• LS
• Supply voltage (Min) (V)
• 4.75
• Supply voltage (Max) (V)
• 5.25
• Input type
• TTL
• Output type
• Push-Pull
• Clock Frequency (MHz)
• 30
• ICC (Max) (uA)
• 6000
• IOL (Max) (mA)
• 8
• IOH (Max) (mA)
• -0.4
• Features
• Negative edge triggered, High speed (tpd 10-50ns), Clear

SN74LS107A的完整型号有：SN74LS107AD、SN74LS107AN、SN74LS107ANSR，以下是这些产品的关键参数及官网采购报价：

SN74LS107AD，工作温度：0 to 70，封装：SOIC (D)-14，包装数量MPQ：50个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74LS107AD的批量USD价格：.778（1000+）

SN74LS107AN，工作温度：0 to 70，封装：PDIP (N)-14，包装数量MPQ：25个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：NIPDAU，TI官网SN74LS107AN的批量USD价格：.895（1000+）

SN74LS107ANSR，工作温度：0 to 70，封装：SO (NS)-14，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74LS107ANSR的批量USD价格：.778（1000+）

14-24-LOGIC-EVM 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。