These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear input.

Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output.

These flip-flops are guaranteed to respond to clock frequencies ranging form 0 to 30 megahertz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 39 milliwatts per flip-flop for the ´273 and 10 milliwatts for the ´LS273.

• Contains Eight Flip-Flops With Single-Rail Outputs
• Buffered Clock and Direct Clear Inputs
• Individual Data Input to Each Flip-Flop
• Applications Include:
  • Buffer/Storage Registers
  • Shift Registers
  • Pattern Generators

• Number of channels (#)
• 8
• Technology Family
• LS
• Supply voltage (Min) (V)
• 4.75
• Supply voltage (Max) (V)
• 5.25
• Input type
• Bipolar
• Output type
• Push-Pull
• Clock Frequency (Max) (MHz)
• 35
• IOL (Max) (mA)
• 8
• IOH (Max) (mA)
• -0.4
• ICC (Max) (uA)
• 27000
• Features
• High speed (tpd 10-50ns)

SN74LS273的完整型号有：SN74LS273DW、SN74LS273DWR、SN74LS273N、SN74LS273NSR，以下是这些产品的关键参数及官网采购报价：

SN74LS273DW，工作温度：0 to 70，封装：SOIC (DW)-20，包装数量MPQ：25个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74LS273DW的批量USD价格：0.36（1000+）

SN74LS273DWR，工作温度：0 to 70，封装：SOIC (DW)-20，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74LS273DWR的批量USD价格：0.3（1000+）

SN74LS273N，工作温度：0 to 70，封装：PDIP (N)-20，包装数量MPQ：20个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：NIPDAU，TI官网SN74LS273N的批量USD价格：0.345（1000+）

SN74LS273NSR，工作温度：0 to 70，封装：SO (NS)-20，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74LS273NSR的批量USD价格：0.33（1000+）

14-24-LOGIC-EVM 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。