These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the '175, 'LS175, and 'S175 feature complementary outputs from each flip-flop.

Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output.

These circuits are fully compatible for use with most TTL circuits.

• '174, 'LS174, 'S174 Contain Six Flip-Flops with Single-Rail Outputs
• '175, 'LS175, 'S175 Contain Four Flip-Flops with Double-Rail Outputs
• Three Performance Ranges Offered: See Table Lower Right
• Buffered Clock and Direct Clear Inputs
• Individual Data Input to Each Flip-Flop
• Applications include:
• Buffer/Storage Registers
• Shift Registers
• Pattern Generators

• Number of channels (#)
• 4
• Technology Family
• S
• Supply voltage (Min) (V)
• 4.75
• Supply voltage (Max) (V)
• 5.25
• Input type
• Bipolar
• Output type
• Push-Pull
• Clock Frequency (Max) (MHz)
• 50
• IOL (Max) (mA)
• 20
• IOH (Max) (mA)
• -1
• ICC (Max) (uA)
• 96000
• Features
• High speed (tpd 10-50ns)

SN74S175的完整型号有：SN74S175D、SN74S175N，以下是这些产品的关键参数及官网采购报价：

SN74S175D，工作温度：0 to 70，封装：SOIC (D)-16，包装数量MPQ：40个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74S175D的批量USD价格：.924（1000+）

SN74S175N，工作温度：0 to 70，封装：PDIP (N)-16，包装数量MPQ：25个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：NIPDAU，TI官网SN74S175N的批量USD价格：1.063（1000+）

14-24-LOGIC-EVM 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。