The SN74LV125A-Q1 quadruple bus buffer gate is designed for 2-V to 5.5-V V_CC operation.

This device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

• Qualified for Automotive Applications
• 2-V to 5.5-V VCC Operation
• Typical VOLP (Output Ground Bounce)<0.8 V at VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)>2.3 V at VCC = 3.3 V, TA = 25°C
• Support Mixed-Mode Voltage Operation on All Ports
• Ioff Supports Partial-Power-Down Mode Operation

• Technology Family
• LV-A
• Supply voltage (Min) (V)
• 2
• Supply voltage (Max) (V)
• 5.5
• Number of channels (#)
• 4
• IOL (Max) (mA)
• 16
• ICC (Max) (uA)
• 20
• IOH (Max) (mA)
• -16
• Input type
• Standard CMOS
• Output type
• 3-State
• Features
• Balanced outputs, Very high speed (tpd 5-10ns), Partial power down (Ioff), Over-voltage tolerant inputs
• Rating
• Automotive

SN74LV125A-Q1的完整型号有：SN74LV125AQRGYRQ1，以下是这些产品的关键参数及官网采购报价：

SN74LV125AQRGYRQ1，工作温度：-40 to 125，封装：VQFN (RGY)-14，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-3-260C-168 HR，引脚镀层/焊球材料：NIPDAU，TI官网SN74LV125AQRGYRQ1的批量USD价格：.121（1000+）

14-24-NL-LOGIC-EVM Generic 14 through 24 pin non-leaded package evaluation module

Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.