TI代理,常备极具竞争力的充足现货
TI哪些型号被关注? TI热门产品型号
TLK6002的基本参数
  • 制造厂商:TI
  • 产品类别:接口
  • 技术类目:其他接口
  • 功能描述:双通道 470Mbps 至 6.25Gbps 多速率收发器
  • 点击这里打开及下载TLK6002的技术文档资料
  • TI代理渠道,提供当日发货、严格的质量标准,满足您的目标价格
快速报价,在行业拥有较高的知名度及影响力
TLK6002的产品详情:

The TLK6002 is a member of a portfolio of multi-gigabit transceivers, intended for use in ultra-high-speed bi-directional point-to-point data transmission systems. It is specifically intended for base station RRH (Remote Radio Head) application, but may also be used in other high speed applications. The TLK6002 supports a serial interface speed of 0.470 Gbps to 6.25 Gbps. Rate support includes all the CPRI and OBSAI rates (0.6144/0.768/1.2288/1.536/2.4576/3.072/4.9152/6.144 Gbps) using a single fixed reference clock frequency (either 122.88 MHz or 153.6 MHz).

TLK6002 20-bit parallel interface operates in 1.5V or 1.8V HSTL single-ended format. The 20-bit interface allows low speed signals on the parallel side and therefore enabling the use of low cost FPGA in the system design. The parallel interface can be programmed to be in SDR (Single Data Rate) or DDR (Double Data Rate) modes. The line rate may be set to full (≤6.25Gbps), half (≤3.75Gbps), quarter (≤1.88Gbps) or eighth (≤0.94Gbps). The line rate can be set using either device inputs or software control registers.

The TLK6002 performs data conversion parallel-to-serial, serial-to-parallel and clock extraction as a physical layer interface device. The serial transceiver interface operates at a maximum serial data rate of 6.25 Gbps.

TLK6002 accepts single-ended HSTL signals at its parallel transmit and receive data buses. If the internal 8B/10B coding and decoding are enabled, TDA/B_[19:0] are latched by TXCLK_A/B and sent to the internal 8b/10b encoder, where the resulting encoded words are serialized and transmitted differentially using a line clock derived from the SERDES reference clock at the desired line rate. If the internal coding and decoding are disabled, TDA/B_[19:0] are defined as 20-bits of data being serialized and transmitted unmodified according to the desired line rate.

The receive direction performs the serial-to-parallel conversion on the input serial data synchronizing the resulting 20-bit parallel data to the recovered byte clock (RXCLK_A/B). The optionally decoded receive data is available on the RDA/B_[19:0] output signals.

The serial transmitter and receiver are implemented using differential Current Mode Logic (CML) with integrated termination resistors.

The TLK6002 provides two local (parallel side) and two remote (serial side) loopback modes for self-test and system diagnostic purposes.

The TLK6002 has an integrated loss of signal (LOS) detection function, which is asserted in conditions where the serial input signal does not have sufficient voltage amplitude (≤75 mVdfpp). Note that the input signal must be ≥150 mVdfpp when loss of signal replacement of the receive datapath data is enabled (register bit 6.6).

TLK6002的优势和特性:
  • Dual Channel 470Mbps to 6.25Gbps Continuous/Multi-Rate Transceiver
  • Supports all CPRI and OBSAI Data Rates
  • Integrated Latency Measurement Function, Accuracy of ±814 ps
  • CPRI/OBSAI Automated Rate Sense (ARS) Function
  • Supports SERDES Operation, 8B/10B Data Modes (20-bit and 16-bit + Controls)
  • 20-bit HSTL Single-Ended Parallel Data Interface (Integrated Source and End Termination)
  • Shared or Independent Reference Clock per Channel
  • Latency/Depth Configurable Transmit and Receive FIFOs.
  • Loopback Capability (Serial and Parallel Side), OBSAI Compliant
  • Supports Serial Retime Operation
  • Supports PRBS (27–1), (223 – 1) and (231–1) and CRPAT Long/Short Generation and Verification
  • Dual Power Supply: 1.0V Core, and 1.5V/1.8V I/O Nominal Supply
  • Serial Side Three Tap Transmit De-emphasis and Receive Adaptive Equalization to Allow Extended Backplane Reach
  • Programmable Output Swing on Serial Output
  • Minimum Receiver Differential Input Thresholds of 100mVdfpp
  • Loss of Signal (LOS) detection (≤75 mVdfpp)
  • Interface to Back Plane, Copper Cables, or Optical Modules
  • Hot Plug Protection
  • JTAG; IEEE 1149.1 /1149.6 Test Interface
  • MDIO; IEEE 802.3 Clause-22 Support
  • 65nm Advanced CMOS Technology
  • Industrial Ambient Operating Temp(–40°C to 85°C) at Full Rate
  • Device Package; 324 PBGA
  • APPLICATIONS
    • WI Infrastructure
    • CPRI and OBSAI Links
    • Proprietary Links
    • Backplane
    • High Speed Point- to-Point Transmission Systems

TLK6002的参数(英文):
  • Operating temperature range (C)
  • -40 to 85
TLK6002具体的完整产品型号参数及价格(美元):

TLK6002的完整型号有:TLK6002ZEU,以下是这些产品的关键参数及官网采购报价:

TLK6002ZEU,工作温度:-40 to 85,封装:BGA (ZEU)-324,包装数量MPQ:84个,MSL 等级/回流焊峰值温度:Level-4-260C-72 HR,引脚镀层/焊球材料:SNAGCU,TI官网TLK6002ZEU的批量USD价格:19.36(1000+)

轻松满足您的TI芯片采购需求
TLK6002的评估套件:

PSPICE-FOR-TI — 适用于 TI 设计和模拟工具的 PSpice

PSpice for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence 的模拟分析引擎。PSpice for TI 可免费使用,包括业内超大的模型库之一,涵盖我们的模拟和电源产品系列以及精选的模拟行为模型。

借助?PSpice for TI 的设计和仿真环境及其内置的模型库,您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案,然后再进行布局和制造,可缩短产品上市时间并降低开发成本。

在?PSpice for TI 设计和仿真工具中,您可以搜索 TI (...)

TINA-TI — 基于 SPICE 的模拟仿真程序

TINA-TI 提供了 SPICE 所有的传统直流、瞬态和频域分析以及更多。TINA 具有广泛的后处理功能,允许您按照希望的方式设置结果的格式。虚拟仪器允许您选择输入波形、探针电路节点电压和波形。TINA 的原理图捕获非常直观 - 真正的“快速入门”。

TINA-TI 安装需要大约 500MB。直接安装,如果想卸载也很容易。我们相信您肯定会爱不释手。

TINA 是德州仪器 (TI) 专有的 DesignSoft 产品。该免费版本具有完整的功能,但不支持完整版 TINA 所提供的某些其他功能。

如需获取可用 TINA-TI 模型的完整列表,请参阅:SpiceRack - 完整列表

需要 HSpice (...)

TI代理|TI中国代理 - 国内领先的TI芯片采购平台
丰富的可销售TI代理库存,专业的销售团队可随时响应您的紧急需求,目标成为有价值的TI代理