CD4086B contains one 4-wide 2-input AND-OR-INVERT gate with an INHIBIT/(EXP\) input and an ENABLE/EXP input. For a 4-wide A-O-I function INHIBIT/(EXP\) is tied to V_SS and ENABLE/EXP to V_DD. See Fig. 10 and its associated explanation for applications where a capability greater than 4-wide is required.

The CD4086B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

• Medium-speed operation - tPHL = 90 ns; tPLH = 140 ns (typ.) at 10 V
• INHIBIT and ENABLE inputs
• Buffered outputs
• 100% tested for quiescent current at 20 V
• Maximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range): 1 V at VDD = 5 V 2 V at VDD = 10 V 2.5 V at VDD = 15 V
• Standardized, symmetrical output characteristics
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"

• Technology Family
• CD4000
• Supply voltage (Min)
• 3
• Supply voltage (Max) (V)
• 18
• Number of channels (#)
• 1
• Inputs per channel
• 2
• IOL (Max) (mA)
• 6.8
• IOH (Max) (mA)
• -6.8
• Input type
• Standard CMOS
• Output type
• Push-Pull
• Features
• Standard speed (tpd > 50ns)
• Data rate (Max) (Mbps)
• 8
• Rating
• Catalog
• Operating temperature range (C)
• -55 to 125

CD4086B的完整型号有：CD4086BE、CD4086BM、CD4086BMT，以下是这些产品的关键参数及官网采购报价：

CD4086BE，工作温度：-55 to 125，封装：PDIP (N)-14，包装数量MPQ：25个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：NIPDAU，TI官网CD4086BE的批量USD价格：.163（1000+）

CD4086BM，工作温度：-55 to 125，封装：SOIC (D)-14，包装数量MPQ：50个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD4086BM的批量USD价格：.143（1000+）

CD4086BMT，工作温度：-55 to 125，封装：SOIC (D)-14，包装数量MPQ：250个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网CD4086BMT的批量USD价格：.143（1000+）

14-24-LOGIC-EVM 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。