These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.

Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.

These circuits are fully compatible for use with most TTL circuits.

• ’ALS174 and ’AS174 Contain Six Flip-Flops With Single-Rail Outputs
• ’ALS175 and ’AS175B Contain Four Flip-Flops With Double-Rail Outputs
• Buffered Clock and Direct-Clear Inputs
• Applications Include:
  • Buffer/Storage Registers
  • Shift Registers
  • Pattern Generators
• Fully Buffered Outputs for Maximum Isolation From External Disturbances (’AS Only)

• Number of channels (#)
• 4
• Technology Family
• AS
• Supply voltage (Min) (V)
• 4.5
• Supply voltage (Max) (V)
• 5.5
• Input type
• Bipolar
• Output type
• Push-Pull
• Clock Frequency (Max) (MHz)
• 100
• IOL (Max) (mA)
• 20
• IOH (Max) (mA)
• -2
• ICC (Max) (uA)
• 34000
• Features
• Very high speed (tpd 5-10ns)

SN74AS175B的完整型号有：SN74AS175BD、SN74AS175BN、SN74AS175BNSR，以下是这些产品的关键参数及官网采购报价：

SN74AS175BD，工作温度：0 to 70，封装：SOIC (D)-16，包装数量MPQ：40个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74AS175BD的批量USD价格：1.794（1000+）

SN74AS175BN，工作温度：0 to 70，封装：PDIP (N)-16，包装数量MPQ：25个，MSL 等级/回流焊峰值温度：N/A for Pkg Type，引脚镀层/焊球材料：NIPDAU，TI官网SN74AS175BN的批量USD价格：2.063（1000+）

SN74AS175BNSR，工作温度：0 to 70，封装：SO (NS)-16，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-1-260C-UNLIM，引脚镀层/焊球材料：NIPDAU，TI官网SN74AS175BNSR的批量USD价格：1.794（1000+）

14-24-LOGIC-EVM 支持 14 到 24 引脚 PW、DB、D、DW、NS、DYY 和 DGV 封装的通用逻辑 EVM

该 EVM 设计用于支持采用 14 至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。