This quadruple bus buffer gate is designed for 0.8-V to 2.7-V V_CC operation, but is designed specifically for 1.6-V to 1.95-V V_CC operation.

The SN74AUC125 contains four independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

• Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
• Ioff Supports Partial-Power-Down Mode Operation
• Sub-1-V Operable
• Max tpd of 2.1 ns at 1.8 V
• Low Power Consumption, 10-A Max ICC
• ±8-mA Output Drive at 1.8 V
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1500-V Charged-Device Model (C101)

• Technology Family
• AUC
• Supply voltage (Min) (V)
• 0.8
• Supply voltage (Max) (V)
• 2.7
• Number of channels (#)
• 4
• IOL (Max) (mA)
• 9
• ICC (Max) (uA)
• 10
• IOH (Max) (mA)
• -9
• Input type
• Standard CMOS
• Output type
• 3-State
• Features
• Balanced outputs, Ultra high speed (tpd <5ns), Partial power down (Ioff), Over-voltage tolerant inputs
• Rating
• Catalog

SN74AUC125的完整型号有：SN74AUC125RGYR，以下是这些产品的关键参数及官网采购报价：

SN74AUC125RGYR，工作温度：-40 to 85，封装：VQFN (RGY)-14，包装数量MPQ：3000个，MSL 等级/回流焊峰值温度：Level-2-260C-1 YEAR，引脚镀层/焊球材料：NIPDAU，TI官网SN74AUC125RGYR的批量USD价格：.396（1000+）

14-24-NL-LOGIC-EVM Generic 14 through 24 pin non-leaded package evaluation module

Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.